<html><head><meta content="text/html; charset=UTF-8" http-equiv="content-type"><style type="text/css">.lst-kix_jxm33uk3v6t-0>li:before{content:"\0025cf  "}.lst-kix_jxm33uk3v6t-1>li:before{content:"\0025cb  "}.lst-kix_jxm33uk3v6t-2>li:before{content:"\0025a0  "}.lst-kix_jxm33uk3v6t-4>li:before{content:"\0025cb  "}.lst-kix_8zn83upigj61-8>li:before{content:"\0025a0  "}.lst-kix_ixbjsfgkr80s-8>li:before{content:"\0025a0  "}.lst-kix_jxm33uk3v6t-3>li:before{content:"\0025cf  "}.lst-kix_8zn83upigj61-6>li:before{content:"\0025cf  "}.lst-kix_8zn83upigj61-5>li:before{content:"\0025a0  "}.lst-kix_8zn83upigj61-7>li:before{content:"\0025cb  "}.lst-kix_jxm33uk3v6t-6>li:before{content:"\0025cf  "}.lst-kix_jxm33uk3v6t-8>li:before{content:"\0025a0  "}.lst-kix_jxm33uk3v6t-5>li:before{content:"\0025a0  "}.lst-kix_8zn83upigj61-3>li:before{content:"\0025cf  "}.lst-kix_8zn83upigj61-4>li:before{content:"\0025cb  "}.lst-kix_jxm33uk3v6t-7>li:before{content:"\0025cb  "}.lst-kix_7xxz4xgukawl-7>li:before{content:"+  "}.lst-kix_ixbjsfgkr80s-1>li:before{content:"\0025cb  "}.lst-kix_ixbjsfgkr80s-2>li:before{content:"\0025a0  "}.lst-kix_7xxz4xgukawl-6>li:before{content:"+  "}.lst-kix_8zn83upigj61-2>li:before{content:"\0025a0  "}.lst-kix_8zn83upigj61-1>li:before{content:"\0025cb  "}.lst-kix_8zn83upigj61-0>li:before{content:"\0025cf  "}.lst-kix_ixbjsfgkr80s-0>li:before{content:"\0025cf  "}.lst-kix_7xxz4xgukawl-8>li:before{content:"+  "}.lst-kix_ixbjsfgkr80s-7>li:before{content:"\0025cb  "}.lst-kix_cm2k39g01xa0-8>li:before{content:"\0025a0  "}.lst-kix_7xxz4xgukawl-1>li:before{content:"+  "}.lst-kix_ixbjsfgkr80s-5>li:before{content:"\0025a0  "}.lst-kix_ixbjsfgkr80s-6>li:before{content:"\0025cf  "}.lst-kix_7xxz4xgukawl-2>li:before{content:"+  "}.lst-kix_ixbjsfgkr80s-3>li:before{content:"\0025cf  "}.lst-kix_lhs3qv964ven-7>li:before{content:"\0025cb  "}.lst-kix_7xxz4xgukawl-3>li:before{content:"+  "}.lst-kix_7xxz4xgukawl-5>li:before{content:"+  "}.lst-kix_lhs3qv964ven-8>li:before{content:"\0025a0  "}.lst-kix_adk9bdggc414-8>li:before{content:"\0025a0  "}.lst-kix_ixbjsfgkr80s-4>li:before{content:"\0025cb  "}.lst-kix_7xxz4xgukawl-4>li:before{content:"+  "}.lst-kix_adk9bdggc414-6>li:before{content:"\0025cf  "}.lst-kix_adk9bdggc414-7>li:before{content:"\0025cb  "}.lst-kix_adk9bdggc414-5>li:before{content:"\0025a0  "}.lst-kix_lhs3qv964ven-6>li:before{content:"\0025cf  "}.lst-kix_aa838qs17hdu-0>li:before{content:"\0025cf  "}.lst-kix_adk9bdggc414-2>li:before{content:"\0025a0  "}.lst-kix_adk9bdggc414-3>li:before{content:"\0025cf  "}.lst-kix_lhs3qv964ven-5>li:before{content:"\0025a0  "}.lst-kix_lhs3qv964ven-4>li:before{content:"\0025cb  "}.lst-kix_adk9bdggc414-4>li:before{content:"\0025cb  "}.lst-kix_lhs3qv964ven-2>li:before{content:"\0025a0  "}.lst-kix_aa838qs17hdu-3>li:before{content:"\0025cf  "}.lst-kix_aa838qs17hdu-4>li:before{content:"\0025cb  "}.lst-kix_lhs3qv964ven-1>li:before{content:"\0025cb  "}.lst-kix_lhs3qv964ven-3>li:before{content:"\0025cf  "}.lst-kix_aa838qs17hdu-1>li:before{content:"\0025cb  "}.lst-kix_aa838qs17hdu-2>li:before{content:"\0025a0  "}.lst-kix_aa838qs17hdu-5>li:before{content:"\0025a0  "}.lst-kix_aa838qs17hdu-6>li:before{content:"\0025cf  "}.lst-kix_adk9bdggc414-1>li:before{content:"\0025cb  "}.lst-kix_adk9bdggc414-0>li:before{content:"\0025cf  "}.lst-kix_lhs3qv964ven-0>li:before{content:"\0025cf  "}.lst-kix_aa838qs17hdu-7>li:before{content:"\0025cb  "}.lst-kix_aa838qs17hdu-8>li:before{content:"\0025a0  "}ul.lst-kix_fpjfm6yu0sfm-4{list-style-type:none}ul.lst-kix_fpjfm6yu0sfm-5{list-style-type:none}ul.lst-kix_fpjfm6yu0sfm-6{list-style-type:none}ul.lst-kix_fpjfm6yu0sfm-7{list-style-type:none}ul.lst-kix_fpjfm6yu0sfm-8{list-style-type:none}ul.lst-kix_fpjfm6yu0sfm-0{list-style-type:none}ul.lst-kix_fpjfm6yu0sfm-1{list-style-type:none}ul.lst-kix_fpjfm6yu0sfm-2{list-style-type:none}ul.lst-kix_fpjfm6yu0sfm-3{list-style-type:none}ul.lst-kix_cm2k39g01xa0-8{list-style-type:none}ul.lst-kix_cm2k39g01xa0-7{list-style-type:none}ul.lst-kix_cm2k39g01xa0-6{list-style-type:none}ul.lst-kix_cm2k39g01xa0-5{list-style-type:none}ul.lst-kix_cm2k39g01xa0-4{list-style-type:none}ul.lst-kix_cm2k39g01xa0-3{list-style-type:none}ul.lst-kix_cm2k39g01xa0-2{list-style-type:none}ul.lst-kix_cm2k39g01xa0-1{list-style-type:none}ul.lst-kix_cm2k39g01xa0-0{list-style-type:none}.lst-kix_cm2k39g01xa0-7>li:before{content:"\0025cb  "}.lst-kix_ie1dgki44qv7-5>li:before{content:"\0025a0  "}.lst-kix_cm2k39g01xa0-5>li:before{content:"\0025a0  "}ul.lst-kix_x259u96bd195-0{list-style-type:none}.lst-kix_ie1dgki44qv7-7>li:before{content:"\0025cb  "}ul.lst-kix_x259u96bd195-1{list-style-type:none}ul.lst-kix_7xxz4xgukawl-0{list-style-type:none}.lst-kix_cm2k39g01xa0-3>li:before{content:"\0025cf  "}ul.lst-kix_x259u96bd195-4{list-style-type:none}ul.lst-kix_x259u96bd195-5{list-style-type:none}ul.lst-kix_x259u96bd195-2{list-style-type:none}ul.lst-kix_x259u96bd195-3{list-style-type:none}ul.lst-kix_x259u96bd195-8{list-style-type:none}ul.lst-kix_x259u96bd195-6{list-style-type:none}ul.lst-kix_x259u96bd195-7{list-style-type:none}.lst-kix_cm2k39g01xa0-1>li:before{content:"\0025cb  "}ul.lst-kix_7xxz4xgukawl-3{list-style-type:none}ul.lst-kix_7xxz4xgukawl-4{list-style-type:none}ul.lst-kix_7xxz4xgukawl-1{list-style-type:none}ul.lst-kix_7xxz4xgukawl-2{list-style-type:none}ul.lst-kix_7xxz4xgukawl-7{list-style-type:none}ul.lst-kix_7xxz4xgukawl-8{list-style-type:none}ul.lst-kix_7xxz4xgukawl-5{list-style-type:none}ul.lst-kix_7xxz4xgukawl-6{list-style-type:none}.lst-kix_ie1dgki44qv7-3>li:before{content:"\0025cf  "}.lst-kix_ie1dgki44qv7-1>li:before{content:"\0025cb  "}ul.lst-kix_r420ekjmc9sd-6{list-style-type:none}ul.lst-kix_r420ekjmc9sd-5{list-style-type:none}ul.lst-kix_r420ekjmc9sd-8{list-style-type:none}ul.lst-kix_r420ekjmc9sd-7{list-style-type:none}ul.lst-kix_r420ekjmc9sd-2{list-style-type:none}ul.lst-kix_r420ekjmc9sd-1{list-style-type:none}ul.lst-kix_r420ekjmc9sd-4{list-style-type:none}.lst-kix_r420ekjmc9sd-0>li:before{content:"\0025cf  "}ul.lst-kix_r420ekjmc9sd-3{list-style-type:none}.lst-kix_r420ekjmc9sd-1>li:before{content:"\0025cb  "}.lst-kix_r420ekjmc9sd-2>li:before{content:"\0025a0  "}.lst-kix_r420ekjmc9sd-3>li:before{content:"\0025cf  "}.lst-kix_r420ekjmc9sd-5>li:before{content:"\0025a0  "}.lst-kix_r420ekjmc9sd-4>li:before{content:"\0025cb  "}.lst-kix_r420ekjmc9sd-8>li:before{content:"\0025a0  "}ul.lst-kix_r420ekjmc9sd-0{list-style-type:none}.lst-kix_r420ekjmc9sd-7>li:before{content:"\0025cb  "}.lst-kix_r420ekjmc9sd-6>li:before{content:"\0025cf  "}ul.lst-kix_aa838qs17hdu-5{list-style-type:none}ul.lst-kix_aa838qs17hdu-6{list-style-type:none}ul.lst-kix_aa838qs17hdu-7{list-style-type:none}ul.lst-kix_aa838qs17hdu-8{list-style-type:none}ul.lst-kix_aa838qs17hdu-1{list-style-type:none}ul.lst-kix_aa838qs17hdu-2{list-style-type:none}ul.lst-kix_aa838qs17hdu-3{list-style-type:none}ul.lst-kix_aa838qs17hdu-4{list-style-type:none}ul.lst-kix_aa838qs17hdu-0{list-style-type:none}ul.lst-kix_8zn83upigj61-8{list-style-type:none}ul.lst-kix_8zn83upigj61-6{list-style-type:none}ul.lst-kix_8zn83upigj61-7{list-style-type:none}ul.lst-kix_8zn83upigj61-4{list-style-type:none}ul.lst-kix_8zn83upigj61-5{list-style-type:none}ul.lst-kix_8zn83upigj61-2{list-style-type:none}ul.lst-kix_8zn83upigj61-3{list-style-type:none}ul.lst-kix_8zn83upigj61-0{list-style-type:none}ul.lst-kix_8zn83upigj61-1{list-style-type:none}ul.lst-kix_ie1dgki44qv7-6{list-style-type:none}ul.lst-kix_ie1dgki44qv7-5{list-style-type:none}ul.lst-kix_ie1dgki44qv7-8{list-style-type:none}ul.lst-kix_ie1dgki44qv7-7{list-style-type:none}.lst-kix_x259u96bd195-1>li:before{content:"\0025cb  "}.lst-kix_x259u96bd195-0>li:before{content:"\0025cf  "}.lst-kix_fpjfm6yu0sfm-1>li:before{content:"\0025cb  "}.lst-kix_x259u96bd195-6>li:before{content:"\0025cf  "}.lst-kix_x259u96bd195-7>li:before{content:"\0025cb  "}.lst-kix_fpjfm6yu0sfm-3>li:before{content:"\0025cf  "}.lst-kix_x259u96bd195-5>li:before{content:"\0025a0  "}.lst-kix_fpjfm6yu0sfm-0>li:before{content:"\0025cf  "}.lst-kix_fpjfm6yu0sfm-4>li:before{content:"\0025cb  "}.lst-kix_x259u96bd195-2>li:before{content:"\0025a0  "}.lst-kix_x259u96bd195-3>li:before{content:"\0025cf  "}ul.lst-kix_ie1dgki44qv7-0{list-style-type:none}ul.lst-kix_ie1dgki44qv7-2{list-style-type:none}ul.lst-kix_ie1dgki44qv7-1{list-style-type:none}.lst-kix_x259u96bd195-4>li:before{content:"\0025cb  "}ul.lst-kix_ie1dgki44qv7-4{list-style-type:none}.lst-kix_fpjfm6yu0sfm-2>li:before{content:"\0025a0  "}ul.lst-kix_ie1dgki44qv7-3{list-style-type:none}.lst-kix_fpjfm6yu0sfm-7>li:before{content:"\0025cb  "}.lst-kix_fpjfm6yu0sfm-8>li:before{content:"\0025a0  "}.lst-kix_fpjfm6yu0sfm-5>li:before{content:"\0025a0  "}.lst-kix_x259u96bd195-8>li:before{content:"\0025a0  "}.lst-kix_fpjfm6yu0sfm-6>li:before{content:"\0025cf  "}ul.lst-kix_jxm33uk3v6t-3{list-style-type:none}ul.lst-kix_jxm33uk3v6t-4{list-style-type:none}ul.lst-kix_jxm33uk3v6t-5{list-style-type:none}ul.lst-kix_jxm33uk3v6t-6{list-style-type:none}ul.lst-kix_jxm33uk3v6t-7{list-style-type:none}ul.lst-kix_lhs3qv964ven-8{list-style-type:none}ul.lst-kix_jxm33uk3v6t-8{list-style-type:none}ul.lst-kix_lhs3qv964ven-4{list-style-type:none}ul.lst-kix_lhs3qv964ven-5{list-style-type:none}ul.lst-kix_lhs3qv964ven-6{list-style-type:none}ul.lst-kix_lhs3qv964ven-7{list-style-type:none}ul.lst-kix_lhs3qv964ven-0{list-style-type:none}ul.lst-kix_lhs3qv964ven-1{list-style-type:none}ul.lst-kix_lhs3qv964ven-2{list-style-type:none}ul.lst-kix_lhs3qv964ven-3{list-style-type:none}ul.lst-kix_adk9bdggc414-5{list-style-type:none}ul.lst-kix_adk9bdggc414-4{list-style-type:none}ul.lst-kix_adk9bdggc414-3{list-style-type:none}ul.lst-kix_adk9bdggc414-2{list-style-type:none}ul.lst-kix_jxm33uk3v6t-0{list-style-type:none}ul.lst-kix_adk9bdggc414-8{list-style-type:none}ul.lst-kix_jxm33uk3v6t-1{list-style-type:none}ul.lst-kix_adk9bdggc414-7{list-style-type:none}ul.lst-kix_jxm33uk3v6t-2{list-style-type:none}ul.lst-kix_adk9bdggc414-6{list-style-type:none}ul.lst-kix_adk9bdggc414-1{list-style-type:none}ul.lst-kix_adk9bdggc414-0{list-style-type:none}.lst-kix_7xxz4xgukawl-0>li:before{content:"+  "}.lst-kix_ie1dgki44qv7-6>li:before{content:"\0025cf  "}.lst-kix_cm2k39g01xa0-6>li:before{content:"\0025cf  "}.lst-kix_cm2k39g01xa0-2>li:before{content:"\0025a0  "}.lst-kix_cm2k39g01xa0-4>li:before{content:"\0025cb  "}.lst-kix_ie1dgki44qv7-8>li:before{content:"\0025a0  "}.lst-kix_cm2k39g01xa0-0>li:before{content:"\0025cf  "}.lst-kix_ie1dgki44qv7-4>li:before{content:"\0025cb  "}ul.lst-kix_ixbjsfgkr80s-1{list-style-type:none}ul.lst-kix_ixbjsfgkr80s-0{list-style-type:none}ul.lst-kix_ixbjsfgkr80s-3{list-style-type:none}.lst-kix_ie1dgki44qv7-2>li:before{content:"\0025a0  "}ul.lst-kix_ixbjsfgkr80s-2{list-style-type:none}ul.lst-kix_ixbjsfgkr80s-5{list-style-type:none}ul.lst-kix_ixbjsfgkr80s-4{list-style-type:none}ul.lst-kix_ixbjsfgkr80s-7{list-style-type:none}.lst-kix_ie1dgki44qv7-0>li:before{content:"\0025cf  "}ul.lst-kix_ixbjsfgkr80s-6{list-style-type:none}ul.lst-kix_ixbjsfgkr80s-8{list-style-type:none}ol{margin:0;padding:0}table td,table th{padding:0}.c6{border-right-style:solid;padding:1.8pt 1.8pt 1.8pt 1.8pt;border-bottom-color:#999999;border-top-width:1pt;border-right-width:1pt;border-left-color:#999999;vertical-align:top;border-right-color:#999999;border-left-width:1pt;border-top-style:solid;border-left-style:solid;border-bottom-width:1pt;width:243pt;border-top-color:#999999;border-bottom-style:solid}.c17{border-right-style:solid;padding:1.8pt 1.8pt 1.8pt 1.8pt;border-bottom-color:#999999;border-top-width:1pt;border-right-width:1pt;border-left-color:#999999;vertical-align:top;border-right-color:#999999;border-left-width:1pt;border-top-style:solid;border-left-style:solid;border-bottom-width:1pt;width:297.8pt;border-top-color:#999999;border-bottom-style:solid}.c30{margin-left:36pt;padding-top:3pt;padding-bottom:0pt;line-height:1.0;orphans:2;widows:2;text-align:left}.c21{color:#000000;font-weight:400;text-decoration:none;vertical-align:baseline;font-size:20pt;font-family:"Arial";font-style:normal}.c23{color:#000000;font-weight:400;text-decoration:none;vertical-align:baseline;font-size:36pt;font-family:"Arial";font-style:normal}.c34{color:#000000;font-weight:400;text-decoration:none;vertical-align:baseline;font-size:16pt;font-family:"Arial";font-style:normal}.c49{margin-left:18pt;padding-top:3pt;padding-bottom:4pt;line-height:1.0;orphans:2;widows:2;text-align:left}.c0{color:#000000;font-weight:400;text-decoration:none;vertical-align:baseline;font-size:8pt;font-family:"Courier New";font-style:normal}.c51{color:#000000;font-weight:400;text-decoration:none;vertical-align:baseline;font-size:14pt;font-family:"Arial";font-style:normal}.c20{color:#434343;font-weight:400;text-decoration:none;vertical-align:baseline;font-size:14pt;font-family:"Arial";font-style:normal}.c46{color:#000000;font-weight:400;text-decoration:none;vertical-align:baseline;font-size:9pt;font-family:"Arial";font-style:normal}.c31{margin-left:18pt;padding-top:3pt;padding-bottom:0pt;line-height:1.0;orphans:2;widows:2;text-align:left}.c11{color:#000000;font-weight:400;text-decoration:none;vertical-align:baseline;font-size:12pt;font-family:"Arial";font-style:normal}.c8{color:#000000;font-weight:400;text-decoration:none;vertical-align:baseline;font-size:9pt;font-family:"Courier New";font-style:normal}.c2{margin-left:36pt;padding-top:0pt;padding-bottom:0pt;line-height:1.15;orphans:2;widows:2;text-align:left}.c1{color:#000000;font-weight:400;text-decoration:none;vertical-align:baseline;font-size:11pt;font-family:"Arial";font-style:normal}.c4{padding-top:0pt;padding-bottom:0pt;line-height:1.15;orphans:2;widows:2;text-align:left}.c26{padding-top:10pt;padding-bottom:0pt;line-height:1.0;orphans:2;widows:2;text-align:left}.c48{color:#000000;text-decoration:none;vertical-align:baseline;font-size:8pt;font-family:"Courier New";font-style:normal}.c28{padding-top:20pt;padding-bottom:6pt;line-height:1.15;page-break-after:avoid;text-align:left;height:20pt}.c22{font-weight:400;text-decoration:none;vertical-align:baseline;font-size:11pt;font-family:"Arial";font-style:normal}.c44{font-weight:400;text-decoration:none;vertical-align:baseline;font-size:20pt;font-family:"Arial";font-style:normal}.c36{padding-top:4pt;padding-bottom:0pt;line-height:1.0;orphans:2;widows:2;text-align:left}.c13{padding-top:18pt;padding-bottom:6pt;line-height:1.15;page-break-after:avoid;text-align:left}.c33{padding-top:16pt;padding-bottom:4pt;line-height:1.15;page-break-after:avoid;text-align:left}.c32{padding-top:20pt;padding-bottom:6pt;line-height:1.15;page-break-after:avoid;text-align:left}.c24{text-decoration-skip-ink:none;-webkit-text-decoration-skip:none;color:#1155cc;text-decoration:underline}.c7{background-color:#d5a6bd;font-size:8pt;font-family:"Courier New";font-weight:400}.c16{color:#595959;text-decoration:none;vertical-align:baseline;font-style:normal}.c14{padding-top:0pt;padding-bottom:0pt;line-height:1.0;text-align:left}.c39{border-spacing:0;border-collapse:collapse;margin-right:auto}.c43{font-size:9pt;font-family:"Courier New";font-weight:400}.c15{font-size:8pt;font-family:"Courier New";font-weight:400}.c40{padding:0;margin:0}.c42{max-width:540pt;padding:36pt 36pt 36pt 36pt}.c3{color:inherit;text-decoration:inherit}.c50{orphans:2;widows:2}.c35{font-size:9.5pt}.c19{background-color:#ffff00}.c41{font-size:36pt}.c47{background-color:#b6d7a8}.c12{height:0pt}.c9{font-weight:700}.c5{color:#0000ff}.c52{height:14pt}.c38{background-color:#ffffff}.c29{font-size:12pt}.c10{height:11pt}.c27{background-color:#d9d9d9}.c37{height:12pt}.c25{background-color:#ffab40}.c45{color:#333333}.c18{padding-left:0pt}.title{padding-top:0pt;color:#000000;font-size:26pt;padding-bottom:3pt;font-family:"Arial";line-height:1.15;page-break-after:avoid;orphans:2;widows:2;text-align:left}.subtitle{padding-top:0pt;color:#666666;font-size:15pt;padding-bottom:16pt;font-family:"Arial";line-height:1.15;page-break-after:avoid;orphans:2;widows:2;text-align:left}li{color:#000000;font-size:11pt;font-family:"Arial"}p{margin:0;color:#000000;font-size:11pt;font-family:"Arial"}h1{padding-top:20pt;color:#000000;font-size:20pt;padding-bottom:6pt;font-family:"Arial";line-height:1.15;page-break-after:avoid;orphans:2;widows:2;text-align:left}h2{padding-top:18pt;color:#000000;font-size:16pt;padding-bottom:6pt;font-family:"Arial";line-height:1.15;page-break-after:avoid;orphans:2;widows:2;text-align:left}h3{padding-top:16pt;color:#434343;font-size:14pt;padding-bottom:4pt;font-family:"Arial";line-height:1.15;page-break-after:avoid;orphans:2;widows:2;text-align:left}h4{padding-top:14pt;color:#666666;font-size:12pt;padding-bottom:4pt;font-family:"Arial";line-height:1.15;page-break-after:avoid;orphans:2;widows:2;text-align:left}h5{padding-top:12pt;color:#666666;font-size:11pt;padding-bottom:4pt;font-family:"Arial";line-height:1.15;page-break-after:avoid;orphans:2;widows:2;text-align:left}h6{padding-top:12pt;color:#666666;font-size:11pt;padding-bottom:4pt;font-family:"Arial";line-height:1.15;page-break-after:avoid;font-style:italic;orphans:2;widows:2;text-align:left}</style></head><body class="c38 c42"><p class="c4"><span class="c9 c41">&nbsp;[riscv-vip]</span><span class="c23">&nbsp; Users&rsquo; Guide</span></p><h1 class="c28" id="h.twfmqfz5d2u0"><span class="c5 c44"></span></h1><p class="c36"><span class="c9 c5"><a class="c3" href="#h.tgyrg7q4ljn9">Overview</a></span><span class="c9 c5">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</span><span class="c9 c5"><a class="c3" href="#h.tgyrg7q4ljn9">1</a></span></p><p class="c26"><span class="c9 c5"><a class="c3" href="#h.731e2dgyudu">License</a></span><span class="c9 c5">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</span><span class="c9 c5"><a class="c3" href="#h.731e2dgyudu">1</a></span></p><p class="c26"><span class="c9 c5"><a class="c3" href="#h.ywq0lv4ofbb3">Community</a></span><span class="c9 c5">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</span><span class="c9 c5"><a class="c3" href="#h.ywq0lv4ofbb3">2</a></span></p><p class="c26"><span class="c9 c5"><a class="c3" href="#h.k494w6kumr5k">Files and directories</a></span><span class="c9 c5">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</span><span class="c9 c5"><a class="c3" href="#h.k494w6kumr5k">2</a></span></p><p class="c26"><span class="c9 c5"><a class="c3" href="#h.8twa0jnbwyf6">Instruction Decode Model</a></span><span class="c9 c5">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</span><span class="c9 c5"><a class="c3" href="#h.8twa0jnbwyf6">3</a></span></p><p class="c26"><span class="c9 c5"><a class="c3" href="#h.3q8qg8s617t4">Core to Coverage plumbing</a></span><span class="c9 c5">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</span><span class="c9 c5"><a class="c3" href="#h.3q8qg8s617t4">4</a></span></p><p class="c31"><span class="c5"><a class="c3" href="#h.j1blccquh4o5">RAW Hazard coverage example</a></span><span class="c5">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</span><span class="c5"><a class="c3" href="#h.j1blccquh4o5">5</a></span></p><p class="c26"><span class="c9 c5"><a class="c3" href="#h.y2c7jss61z8d">Running riscv-vip unit tests</a></span><span class="c9 c5">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</span><span class="c9 c5"><a class="c3" href="#h.y2c7jss61z8d">6</a></span></p><p class="c31"><span class="c5"><a class="c3" href="#h.md8ehg2r1vjs">Instruction unit tests</a></span><span class="c5">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</span><span class="c5"><a class="c3" href="#h.md8ehg2r1vjs">6</a></span></p><p class="c31"><span class="c5"><a class="c3" href="#h.vfsts1ixyjl1">Instruction History unit tests</a></span><span class="c5">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</span><span class="c5"><a class="c3" href="#h.vfsts1ixyjl1">8</a></span></p><p class="c31"><span class="c5"><a class="c3" href="#h.n6xp8fmn6aw1">HEX file analyzer unit tests</a></span><span class="c5">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</span><span class="c5"><a class="c3" href="#h.n6xp8fmn6aw1">8</a></span></p><p class="c30"><span class="c5"><a class="c3" href="#h.eo7whbwx6x75">View the functional coverage of scanning the HEX files</a></span><span class="c5">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</span><span class="c5"><a class="c3" href="#h.eo7whbwx6x75">9</a></span></p><p class="c30"><span class="c5"><a class="c3" href="#h.frtdl08uxjvc">Generating the HEX files from source, for the hex_file_analyzer</a></span><span class="c5">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</span><span class="c5"><a class="c3" href="#h.frtdl08uxjvc">10</a></span></p><p class="c26"><span class="c5 c9"><a class="c3" href="#h.usth6hj7su54">Adding riscv-vip to an existing RISC-V core</a></span><span class="c9 c5">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</span><span class="c9 c5"><a class="c3" href="#h.usth6hj7su54">11</a></span></p><p class="c30"><span class="c5"><a class="c3" href="#h.tqcs6dcoa7z4">Update your build process to compile and include riscv-vip files</a></span><span class="c5">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</span><span class="c5"><a class="c3" href="#h.tqcs6dcoa7z4">11</a></span></p><p class="c30"><span class="c5"><a class="c3" href="#h.cl9dy39kyl5w">Update your testbench</a></span><span class="c5">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</span><span class="c5"><a class="c3" href="#h.cl9dy39kyl5w">11</a></span></p><p class="c31"><span class="c5"><a class="c3" href="#h.hk2zvn4lklf8">Simulator flags</a></span><span class="c5">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</span><span class="c5"><a class="c3" href="#h.hk2zvn4lklf8">14</a></span></p><p class="c49"><span class="c5"><a class="c3" href="#h.fxza2dadr22z">Locating the trace file</a></span><span class="c5">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</span><span class="c5"><a class="c3" href="#h.fxza2dadr22z">14</a></span></p><p class="c4 c10"><span class="c22 c5"></span></p><h1 class="c32" id="h.tgyrg7q4ljn9"><span class="c21">Overview</span></h1><p class="c4"><span class="c11">For pre-silicon developers of RISC-V systems, the riscv-vip project:</span></p><ul class="c40 lst-kix_x259u96bd195-0 start"><li class="c2 c18"><span class="c11">helps with pre-si verification and debug</span></li><li class="c2 c18"><span class="c11">provides a growing checklist of important corner cases for objectively measuring functional coverage</span></li><li class="c2 c18"><span class="c11">works with existing tools and flows - open-source in pure SystemVerilog (with a UVM option)</span></li><li class="c2 c18"><span class="c29">manages complexity through object orientation</span></li></ul><h1 class="c32" id="h.731e2dgyudu"><span class="c21">License</span></h1><p class="c4"><span class="c1">The riscv-vip project is licensed under the Apache Version 2.0 license. &nbsp;</span></p><p class="c4 c10"><span class="c1"></span></p><p class="c4"><span>The hex files committed in the riscv-vip/riscv_tests_hexgen/build/ directory are generated from assembly *.S files from the riscv-test project, available at </span><span class="c24"><a class="c3" href="https://www.google.com/url?q=https://github.com/riscv/riscv-tests&amp;sa=D&amp;ust=1547000476220000">https://github.com/riscv/riscv-tests</a></span><span>&nbsp;and licensed under its own license. </span></p><h1 class="c32" id="h.ywq0lv4ofbb3"><span class="c21">Community </span></h1><ul class="c40 lst-kix_8zn83upigj61-0 start"><li class="c2 c18"><span class="c1">collectively improve the quality of RISC-V systems</span></li><li class="c2 c18"><span class="c1">define a functional coverage model based on group thinking and experience</span></li></ul><h1 class="c32" id="h.k494w6kumr5k"><span class="c21">Files and directories</span></h1><p class="c4"><span class="c1">The main files and directories are shown in the following table.</span></p><p class="c4 c10"><span class="c8"></span></p><a id="t.10df22d1ee2e2cc272004c3d745878536c3b699e"></a><a id="t.0"></a><table class="c39"><tbody><tr class="c12"><td class="c6 c27" colspan="1" rowspan="1"><p class="c14"><span class="c8">riscv-vip/</span></p></td><td class="c17 c27" colspan="1" rowspan="1"><p class="c14"><span class="c8">Root of repo</span></p></td></tr><tr class="c12"><td class="c6" colspan="1" rowspan="1"><p class="c14"><span class="c8">riscv-vip/LICENSE.txt</span></p></td><td class="c17" colspan="1" rowspan="1"><p class="c14"><span class="c8">Apache License</span></p></td></tr><tr class="c12"><td class="c6" colspan="1" rowspan="1"><p class="c14"><span class="c8">riscv-vip/README.md</span></p></td><td class="c17" colspan="1" rowspan="1"><p class="c14"><span class="c8">Readme file</span></p></td></tr><tr class="c12"><td class="c6" colspan="1" rowspan="1"><p class="c14"><span class="c8">riscv-vip/RELEASE.txt</span></p></td><td class="c17" colspan="1" rowspan="1"><p class="c14"><span class="c8">Release notes</span></p></td></tr><tr class="c12"><td class="c6 c27" colspan="1" rowspan="1"><p class="c14"><span class="c8">riscv-vip/doc/</span></p></td><td class="c17 c27" colspan="1" rowspan="1"><p class="c14"><span class="c8">Documentation dir</span></p></td></tr><tr class="c12"><td class="c6" colspan="1" rowspan="1"><p class="c14"><span class="c8">riscv-vip/doc/index.html</span></p></td><td class="c17" colspan="1" rowspan="1"><p class="c14"><span class="c43">Open in your web browser for documentation. &nbsp;Also available at </span><span class="c24 c43"><a class="c3" href="https://www.google.com/url?q=https://jerralph.github.io/riscv-vip/doc/index.html&amp;sa=D&amp;ust=1547000476225000">https://jerralph.github.io/riscv-vip/doc/index.html</a></span><span class="c8">&nbsp;</span></p></td></tr><tr class="c37"><td class="c6 c27" colspan="1" rowspan="1"><p class="c14"><span class="c8">riscv-vip/src/</span></p></td><td class="c17 c27" colspan="1" rowspan="1"><p class="c14"><span class="c8">Source folder</span></p></td></tr><tr class="c12"><td class="c6" colspan="1" rowspan="1"><p class="c14"><span class="c8">riscv-vip/src/csrs.sv</span></p></td><td class="c17" colspan="1" rowspan="1"><p class="c14"><span class="c8">Passive CSR model and white box monitor for CSRs. &nbsp;Not currently integrated into UVC and model - FUTURE. &nbsp;</span></p></td></tr><tr class="c12"><td class="c6" colspan="1" rowspan="1"><p class="c14"><span class="c8">riscv-vip/src/csrs_unit_test.sv</span></p></td><td class="c17" colspan="1" rowspan="1"><p class="c14"><span class="c8">Unit test for csrs.sv</span></p></td></tr><tr class="c12"><td class="c6" colspan="1" rowspan="1"><p class="c14"><span class="c8">riscv-vip/src/decoder.svh</span></p></td><td class="c17" colspan="1" rowspan="1"><p class="c14"><span class="c8">Decoder class</span></p></td></tr><tr class="c12"><td class="c6" colspan="1" rowspan="1"><p class="c14"><span class="c8">riscv-vip/src/hex_file_analyzer.svh</span></p></td><td class="c17" colspan="1" rowspan="1"><p class="c14"><span class="c8">Hex file Analyzer class</span></p></td></tr><tr class="c12"><td class="c6" colspan="1" rowspan="1"><p class="c14"><span class="c8">riscv-vip/src/hex_file_analyzer_unit_test.sv</span></p></td><td class="c17" colspan="1" rowspan="1"><p class="c14"><span class="c8">Hex file Analyzer unit tests</span></p></td></tr><tr class="c12"><td class="c6" colspan="1" rowspan="1"><p class="c14"><span class="c8">riscv-vip/src/inst_history.svh</span></p></td><td class="c17" colspan="1" rowspan="1"><p class="c14"><span class="c8">Instruction history class and the raw_hazard_examiner class, which covers interesting read after write (RAW) register hazards between instructions. </span></p></td></tr><tr class="c12"><td class="c6" colspan="1" rowspan="1"><p class="c14"><span class="c8">riscv-vip/src/inst_history_unit_test.sv</span></p></td><td class="c17" colspan="1" rowspan="1"><p class="c14"><span class="c8">Unit tests for inst_history.svh</span></p></td></tr><tr class="c12"><td class="c6" colspan="1" rowspan="1"><p class="c14"><span class="c8">riscv-vip/src/instruction.svh</span></p></td><td class="c17" colspan="1" rowspan="1"><p class="c14"><span class="c8">Instruction Classes</span></p></td></tr><tr class="c12"><td class="c6" colspan="1" rowspan="1"><p class="c14"><span class="c8">riscv-vip/src/instruction_unit_test.sv</span></p></td><td class="c17" colspan="1" rowspan="1"><p class="c14"><span class="c8">Instruction unit tests</span></p></td></tr><tr class="c12"><td class="c6" colspan="1" rowspan="1"><p class="c14"><span class="c8">riscv-vip/src/Makefile</span></p></td><td class="c17" colspan="1" rowspan="1"><p class="c14"><span class="c8">Makefile for running unit tests</span></p></td></tr><tr class="c12"><td class="c6" colspan="1" rowspan="1"><p class="c14"><span class="c8">riscv-vip/src/pipeline.svh</span></p></td><td class="c17" colspan="1" rowspan="1"><p class="c14"><span class="c8">Passive instruction pipeline model. &nbsp;Placeholder currently, not much here yet. &nbsp;Will be used for identifying data hazards, etc. FUTURE. </span></p></td></tr><tr class="c12"><td class="c6" colspan="1" rowspan="1"><p class="c14"><span class="c8">riscv-vip/src/reg_fetcher.svh</span></p></td><td class="c17" colspan="1" rowspan="1"><p class="c14"><span class="c8">Register file value fetcher. Given an instruction, uses regfile to set the data values of the source registers used by the instruction. </span></p></td></tr><tr class="c12"><td class="c6" colspan="1" rowspan="1"><p class="c14"><span class="c8">riscv-vip/src/reg_fetcher_unit_test.sv</span></p></td><td class="c17" colspan="1" rowspan="1"><p class="c14"><span class="c8">Regfetcher unit test</span></p></td></tr><tr class="c12"><td class="c6" colspan="1" rowspan="1"><p class="c14"><span class="c8">riscv-vip/src/regfile.svh</span></p></td><td class="c17" colspan="1" rowspan="1"><p class="c14"><span class="c8">Passive regfile model and white box monitor.</span></p></td></tr><tr class="c12"><td class="c6" colspan="1" rowspan="1"><p class="c14"><span class="c8">riscv-vip/src/regfile_unit_test.sv</span></p></td><td class="c17" colspan="1" rowspan="1"><p class="c14"><span class="c8">Regfile unit test</span></p></td></tr><tr class="c52"><td class="c6" colspan="1" rowspan="1"><p class="c14"><span class="c8">riscv-vip/src/riscv_vip_class_pkg.sv</span></p></td><td class="c17" colspan="1" rowspan="1"><p class="c14"><span class="c8">Package of non-UVM classes.</span></p></td></tr><tr class="c12"><td class="c6" colspan="1" rowspan="1"><p class="c14"><span class="c8">riscv-vip/src/riscv_vip_csr_if.sv</span></p></td><td class="c17" colspan="1" rowspan="1"><p class="c14"><span class="c8">CSR whitebox interface </span></p></td></tr><tr class="c12"><td class="c6" colspan="1" rowspan="1"><p class="c14"><span class="c8">riscv-vip/src/riscv_vip_defines.svh</span></p></td><td class="c17" colspan="1" rowspan="1"><p class="c14"><span class="c8">`defines</span></p></td></tr><tr class="c12"><td class="c6" colspan="1" rowspan="1"><p class="c14"><span class="c8">riscv-vip/src/risc_vip.do</span></p></td><td class="c17" colspan="1" rowspan="1"><p class="c14"><span class="c8">Mentor do file</span></p></td></tr><tr class="c12"><td class="c6" colspan="1" rowspan="1"><p class="c14"><span class="c8">riscv-vip/src/riscv_vip.f</span></p></td><td class="c17" colspan="1" rowspan="1"><p class="c14"><span class="c8">File list</span></p></td></tr><tr class="c12"><td class="c6" colspan="1" rowspan="1"><p class="c14"><span class="c8">riscv-vip/src/riscv_vip_inst_if.sv</span></p></td><td class="c17" colspan="1" rowspan="1"><p class="c14"><span class="c8">Instruction interface file</span></p></td></tr><tr class="c12"><td class="c6" colspan="1" rowspan="1"><p class="c14"><span class="c8">riscv-vip/src/riscv_vip_pkg.sv</span></p></td><td class="c17" colspan="1" rowspan="1"><p class="c14"><span class="c8">Package of parameters, types, structures, constants</span></p></td></tr><tr class="c12"><td class="c6" colspan="1" rowspan="1"><p class="c14"><span class="c8">riscv-vip/src/riscv_vip_regfile_if.sv</span></p></td><td class="c17" colspan="1" rowspan="1"><p class="c14"><span class="c8">Regfile whitebox interface </span></p></td></tr><tr class="c12"><td class="c6 c27" colspan="1" rowspan="1"><p class="c14"><span class="c8">riscv-vip/src/uvm/</span></p></td><td class="c17 c27" colspan="1" rowspan="1"><p class="c14"><span class="c8">Folder containing UVM related files</span></p></td></tr><tr class="c12"><td class="c6" colspan="1" rowspan="1"><p class="c14"><span class="c8">riscv-vip/src/uvm/i32_agent.svh</span></p></td><td class="c17" colspan="1" rowspan="1"><p class="c14"><span class="c8">Passive RV32I UVM Agent</span></p></td></tr><tr class="c12"><td class="c6" colspan="1" rowspan="1"><p class="c14"><span class="c8">riscv-vip/src/uvm/i32_agent_unit_test.sv</span></p></td><td class="c17" colspan="1" rowspan="1"><p class="c14"><span class="c8">Unit test for RV32I UVM agent</span></p></td></tr><tr class="c12"><td class="c6" colspan="1" rowspan="1"><p class="c14"><span class="c8">riscv-vip/src/uvm/i32_cov_subscriber.svh</span></p></td><td class="c17" colspan="1" rowspan="1"><p class="c14"><span class="c8">RV32I Coverage subscriber</span></p></td></tr><tr class="c12"><td class="c6" colspan="1" rowspan="1"><p class="c14"><span class="c8">riscv-vip/src/uvm/i32_item.svh</span></p></td><td class="c17" colspan="1" rowspan="1"><p class="c14"><span class="c8">RV32I Transaction item</span></p></td></tr><tr class="c12"><td class="c6" colspan="1" rowspan="1"><p class="c14"><span class="c8">riscv-vip/src/uvm/i32_monitor.svh</span></p></td><td class="c17" colspan="1" rowspan="1"><p class="c14"><span class="c8">RV32I Passive monitor</span></p></td></tr><tr class="c12"><td class="c6" colspan="1" rowspan="1"><p class="c14"><span class="c8">riscv-vip/src/uvm/Makefile</span></p></td><td class="c17" colspan="1" rowspan="1"><p class="c14"><span class="c8">Makefile for running tests</span></p></td></tr><tr class="c12"><td class="c6" colspan="1" rowspan="1"><p class="c14"><span class="c8">riscv-vip/src/uvm/riscv_vip_uvc.f</span></p></td><td class="c17" colspan="1" rowspan="1"><p class="c14"><span class="c8">UVC file list</span></p></td></tr><tr class="c12"><td class="c6" colspan="1" rowspan="1"><p class="c14"><span class="c8">riscv-vip/src/uvm/riscv_vip_uvc_pkg.sv</span></p></td><td class="c17" colspan="1" rowspan="1"><p class="c14"><span class="c8">UVC package</span></p></td></tr><tr class="c12"><td class="c6" colspan="1" rowspan="1"><p class="c14"><span class="c8">riscv-vip/src/uvm/uvc_env.svh</span></p></td><td class="c17" colspan="1" rowspan="1"><p class="c14"><span class="c8">UVC environment</span></p></td></tr><tr class="c12"><td class="c6" colspan="1" rowspan="1"><p class="c14"><span class="c8">riscv-vip/src/uvm/uvc_env_unit_test.sv</span></p></td><td class="c17" colspan="1" rowspan="1"><p class="c14"><span class="c8">UVC environment unit test</span></p></td></tr><tr class="c12"><td class="c6 c27" colspan="1" rowspan="1"><p class="c14"><span class="c8">riscv-vip/riscv_tests_hexgen/</span></p></td><td class="c17 c27" colspan="1" rowspan="1"><p class="c14"><span class="c8">Dir for building HEX files from riscv-test source.</span></p></td></tr><tr class="c12"><td class="c6 c27" colspan="1" rowspan="1"><p class="c14"><span class="c8">riscv-vip/riscv_tests_hexgen/build/</span></p></td><td class="c17 c27" colspan="1" rowspan="1"><p class="c14"><span class="c8">Build dir populated by running make</span></p></td></tr><tr class="c12"><td class="c6" colspan="1" rowspan="1"><p class="c14"><span class="c8">riscv-vip/riscv_tests_hexgen/build/hex_files.txt</span></p></td><td class="c17" colspan="1" rowspan="1"><p class="c14"><span class="c8">List of HEX files for reading in by the hex_file_analyzer class.</span></p></td></tr><tr class="c12"><td class="c6" colspan="1" rowspan="1"><p class="c14"><span class="c8">riscv-vip/riscv_tests_hexgen/build/*.hex</span></p></td><td class="c17" colspan="1" rowspan="1"><p class="c14 c50"><span class="c43">Pre-committed HEX files for RV32UI tests generated from the riscv-tests project assembly files from </span><span class="c24 c43"><a class="c3" href="https://www.google.com/url?q=https://github.com/riscv/riscv-tests&amp;sa=D&amp;ust=1547000476248000">https://github.com/riscv/riscv-tests</a></span><span class="c8">&nbsp;</span></p></td></tr><tr class="c12"><td class="c6" colspan="1" rowspan="1"><p class="c14"><span class="c8">riscv-vip/riscv_tests_hexgen/link.ld</span></p></td><td class="c17" colspan="1" rowspan="1"><p class="c14"><span class="c8">Linker script for generating HEX files from riscv-tests assembly.</span></p></td></tr><tr class="c12"><td class="c6" colspan="1" rowspan="1"><p class="c14"><span class="c8">riscv-vip/riscv_tests_hexgen/Makefile</span></p></td><td class="c17" colspan="1" rowspan="1"><p class="c14"><span class="c8">Makefile for generated HEX files from riscv-tests assembly</span></p></td></tr></tbody></table><p class="c4 c10"><span class="c0"></span></p><h1 class="c32" id="h.8twa0jnbwyf6"><span class="c21">Instruction Decode Model</span></h1><p class="c4"><span class="c1">The decoder class decodes raw bits into the riscv-vip instruction decode model. &nbsp;The instruction class hierarchy is as follows where the specific formats are derived from the general inst32 class. &nbsp;For simplicity, many methods are omitted from this diagram.</span></p><p class="c4 c10"><span class="c1"></span></p><p class="c4"><span style="overflow: hidden; display: inline-block; margin: 0.00px 0.00px; border: 0.00px solid #000000; transform: rotate(0.00rad) translateZ(0px); -webkit-transform: rotate(0.00rad) translateZ(0px); width: 624.00px; height: 318.00px;"><img alt="" src="images/image4.jpg" style="width: 624.00px; height: 468.00px; margin-left: 0.00px; margin-top: 0.00px; transform: rotate(0.00rad) translateZ(0px); -webkit-transform: rotate(0.00rad) translateZ(0px);" title=""></span></p><p class="c4"><span class="c1">For example, consider the following code:</span></p><p class="c4 c10"><span class="c1"></span></p><p class="c4"><span class="c0">&nbsp; &nbsp; &nbsp; &nbsp;decoder decoder0 = new();</span></p><p class="c4"><span class="c0">&nbsp; &nbsp; &nbsp; &nbsp;bit[31:0] inst_bits = 32&#39;hfff08193; &nbsp; &nbsp;</span></p><p class="c4"><span class="c0">&nbsp; &nbsp; &nbsp; &nbsp;inst32 i32 = decoder0.decode_inst32(inst_bits);</span></p><p class="c4"><span class="c0">&nbsp; &nbsp; &nbsp; &nbsp;$display(&quot;decode of 0x%0H is [ %s ]&quot;, inst_bits, i32.to_string());</span></p><p class="c4 c10"><span class="c1"></span></p><p class="c4"><span class="c1">This will display the following output:</span></p><p class="c4 c10"><span class="c1"></span></p><p class="c2"><span class="c15">&nbsp;decode of </span><span class="c15">0xfff08193 is [ fff08193 I ADDI X3_GP, X1_RA, -1 ]</span></p><p class="c4 c10"><span class="c1"></span></p><p class="c4"><span class="c1">This is an I format add immediate, addi, instruction with an immediate value of -1, using x1 as the source and x3 for the destination register. &nbsp;For more details on instruction formats and how this is encoded/decoded, refer to the RISC-V specification.</span></p><p class="c4 c10"><span class="c1"></span></p><p class="c4"><span class="c1">In the inst32_iformat class, there is a coverage bin for non-special I instructions with immediates of -1 (or all 1s in binary), as shown below:</span></p><p class="c4 c10"><span class="c1"></span></p><p class="c4"><span class="c0">&nbsp; &nbsp; i32i_imm_cp : coverpoint imm iff ((inst inside {I_NONSPECIAL_INSTS})) {</span></p><p class="c4"><span class="c0">&nbsp; &nbsp; &nbsp; bins basics[] = {0,1,2,4};</span></p><p class="c4"><span class="c0">&nbsp; &nbsp; &nbsp; bins max_pos = &nbsp;{`IMM_MAX_POS(imm)};</span></p><p class="c4"><span class="c15">&nbsp; &nbsp; &nbsp; </span><span class="c9 c48">bins all_ones = {`IMM_ALL_ONES(imm)};</span></p><p class="c4"><span class="c15">&nbsp; &nbsp; &nbsp; bins min_neg = &nbsp;{</span><span class="c15">`IMM_MIN_NEG</span><span class="c0">(imm)}; </span></p><p class="c4"><span class="c0">&nbsp; &nbsp; }</span></p><p class="c4 c10"><span class="c1"></span></p><p class="c4"><span class="c1">Non-special refers to standard I format instructions like ADDI and ANDI. &nbsp;Non-special I instructions include all I instructions except {SLLI, SRLI, SRAI, FENCE, FENCE.I, ECALL, EBREAK, CSRR*}, which are special -- they have something special/different about them and need to be covered a bit differently.</span></p><p class="c4 c10"><span class="c1"></span></p><p class="c4"><span class="c1">The following illustrates how coverage is sampled and a generic inst32 is cast to a specific inst32_iformat class:</span></p><p class="c4 c10"><span class="c1"></span></p><p class="c4"><span class="c0">&nbsp; &nbsp; &nbsp; &nbsp; //Cast the general inst32 into the more specific inst32_iformat once we&#39;re sure it</span></p><p class="c4"><span class="c0">&nbsp; &nbsp; &nbsp; &nbsp; //really is an I format. &nbsp;The coverage should be 0 before sampling then</span></p><p class="c4"><span class="c0">&nbsp; &nbsp; &nbsp; &nbsp; //have one bin hit after sampling</span></p><p class="c4 c10"><span class="c0"></span></p><p class="c4"><span class="c0">&nbsp; &nbsp; &nbsp; &nbsp; inst32_iformat i32i; &nbsp; &nbsp; &nbsp; &nbsp; </span></p><p class="c4"><span class="c0">&nbsp; &nbsp; &nbsp; &nbsp; assert(i32.is_i_format());</span></p><p class="c4"><span class="c0">&nbsp; &nbsp; &nbsp; &nbsp; $cast(i32i,i32);</span></p><p class="c4"><span class="c0">&nbsp; &nbsp; &nbsp; &nbsp; cov = i32i.get_nonspecial_imm_cov(); </span></p><p class="c4"><span class="c0">&nbsp; &nbsp; &nbsp; &nbsp; assert(cov == 0); &nbsp; &nbsp; &nbsp; &nbsp; </span></p><p class="c4"><span class="c0">&nbsp; &nbsp; &nbsp; &nbsp; i32i.sample_cov();</span></p><p class="c4"><span class="c0">&nbsp; &nbsp; &nbsp; &nbsp; cov = i32i.get_nonspecial_imm_cov();</span></p><p class="c4"><span class="c15">&nbsp; &nbsp; &nbsp; &nbsp; $display(&quot;after sample_cov of 0x%0H get_nonspecial_imm_cov() yields %0f&quot;, inst_bits, cov);</span></p><p class="c4 c10"><span class="c1"></span></p><p class="c4"><span class="c1">The resulting output is:</span></p><p class="c4 c10"><span class="c1"></span></p><p class="c2"><span class="c15">after sample_cov of 0xfff08193 get_nonspecial_imm_cov() yields 14.285714</span></p><p class="c4 c10"><span class="c1"></span></p><p class="c4"><span>This is the coverage we expect since 1/7 coverage bins are hit. Such coverage will also show up in the </span><span>simulator&rsquo;s coverage database</span><span class="c1">&nbsp;and analysis interfaces.</span></p><h1 class="c32" id="h.3q8qg8s617t4"><span class="c21">Core to Coverage plumbing</span></h1><p class="c4"><span class="c1">The riscv-vip monitors attached to the internal interfaces of the RISC-V core RTL to extract the instruction, address, and register values. &nbsp;From these interfaces, the riscv-vip object model and the instruction history are populated and the contained functional coverage becomes available. &nbsp;The following diagram illustrates the plumbing in a conceptual, simplified way.</span></p><p class="c14"><span style="overflow: hidden; display: inline-block; margin: 0.00px 0.00px; border: 0.00px solid #000000; transform: rotate(0.00rad) translateZ(0px); -webkit-transform: rotate(0.00rad) translateZ(0px); width: 720.00px; height: 318.67px;"><img alt="" src="images/image2.png" style="width: 720.00px; height: 318.67px; margin-left: 0.00px; margin-top: 0.00px; transform: rotate(0.00rad) translateZ(0px); -webkit-transform: rotate(0.00rad) translateZ(0px);" title=""></span></p><p class="c4 c10"><span class="c1"></span></p><h2 class="c13" id="h.j1blccquh4o5"><span class="c34">RAW Hazard coverage example</span></h2><p class="c4"><span class="c1">The Instruction History class is used to capture coverage of important inter-instruction cases, like a read-after-write (RAW) hazard.The RAW hazard is when an instruction uses a source register that has a stale value in the register file and its value is in the process of getting updated by an earlier instruction in the pipeline. </span></p><p class="c4 c10"><span class="c1"></span></p><p class="c4"><span class="c1">Consider the following coverage requirement:</span></p><p class="c4 c10"><span class="c1"></span></p><p class="c2"><span class="c1">Cross all RV32I instructions that use rs1 and/or rs2 with case they have a read after write (RAW) data hazard, whereby a previous instruction {1,2,3} cycles ago modified the reg that is used by the instruction for {rs1 only, rs2 only, and both rs1/2} cases. &nbsp;For instructions that only have rs1 ignore the irrelevant bins.</span></p><p class="c2 c10"><span class="c1"></span></p><p class="c4"><span class="c1">The SystemVerilog code in the inst_history.svh file to achieve this coverage is as follows:</span></p><p class="c4 c10"><span class="c1"></span></p><p class="c14"><span class="c0">covergroup raw_cg;</span></p><p class="c14"><span class="c0">&nbsp; &nbsp; read_inst_cp : coverpoint m_rd_inst.get_inst_enum(){</span></p><p class="c14"><span class="c0">&nbsp; &nbsp; &nbsp; ignore_bins ignore_has_no_rs_insts = {`INSTS_WITH_NO_RS_LIST};</span></p><p class="c14"><span class="c0">&nbsp; &nbsp; &nbsp; ignore_bins unknown_inst = {UNKNOWN_INST};</span></p><p class="c14"><span class="c0">&nbsp; &nbsp; } </span></p><p class="c14"><span class="c0">&nbsp; &nbsp; rs_case_cp : coverpoint raw_rs_case iff(raw_rs_case != NONE){</span></p><p class="c14"><span class="c0">&nbsp; &nbsp; &nbsp; ignore_bins ignore_none = {NONE};</span></p><p class="c14"><span class="c0">&nbsp; &nbsp; }</span></p><p class="c14"><span class="c0">&nbsp; &nbsp; cyc_apart_cp : coverpoint m_cycles_apart {</span></p><p class="c14"><span class="c0">&nbsp; &nbsp; &nbsp; bins cycs[] = {[1:MAX_CYCLES_APART_OF_INTEREST]}; </span></p><p class="c14"><span class="c0">&nbsp; &nbsp; }</span></p><p class="c14"><span class="c0">&nbsp; &nbsp; inst_x_rs_case_x_cyc_apart : cross read_inst_cp, rs_case_cp, cyc_apart_cp{</span></p><p class="c14"><span class="c0">&nbsp; &nbsp; &nbsp; //for insts w/o rs2 fields, only look at the RS1 case (ignore rs2 cases). </span></p><p class="c14"><span class="c0">&nbsp; &nbsp; &nbsp; ignore_bins ignore_rs2_for_non_rs2_insts = inst_x_rs_case_x_cyc_apart with </span></p><p class="c14"><span class="c0">&nbsp; &nbsp; &nbsp; &nbsp; ( !(read_inst_cp inside {`INSTS_W_RS2_LIST}) &amp;&amp; (rs_case_cp != RS1_ONLY) );</span></p><p class="c14"><span class="c15">&nbsp; &nbsp; }</span></p><p class="c14"><span class="c15 c16">}</span></p><p class="c4 c10"><span class="c1"></span></p><p class="c4"><span class="c1">The read_inst_cp has 37 bins &nbsp;-- 47 RV32I instruction less 10 ignored since they don&rsquo;t have source register fields. &nbsp;</span></p><p class="c4 c10"><span class="c1"></span></p><p class="c4"><span class="c1">The rs_case_cp has 3 bins -- RS1_ONLY, RS1_ONLY, and RS1ANDRS2;</span></p><p class="c4 c10"><span class="c1"></span></p><p class="c4"><span class="c1">The cyc_apart_cp has 3 bins, for instructions that are 1, 2 or 3 cycles apart.</span></p><p class="c4 c10"><span class="c1"></span></p><p class="c4"><span class="c1">The cross, inst_x_rs_case_x_cyc_apart has 225 bins. &nbsp;19/37 have rs1 and rs2 fields, and 18/37 have only rs2, so the cross multiplies out as 19*3*3 + 18*3*1 = 225.</span></p><p class="c4 c10"><span class="c1"></span></p><p class="c4"><span class="c1">As an illustrative example, consider the following sequence of instructions and the related coverage coverage report for the inst_x_rs_case_x_cyc_apart cross coverage. </span></p><p class="c4 c10"><span class="c1"></span></p><p class="c14"><span class="c0">0 401080b3 R SUB X1, X1, X1 </span></p><p class="c14"><span class="c15">1 40210133 R SUB </span><span class="c15 c25">X2</span><span class="c0">, X2, X2 </span></p><p class="c14"><span class="c15">2 403181b3 R SUB </span><span class="c15 c47">X3</span><span class="c0">, X3, X3 </span></p><p class="c14"><span class="c0">3 40420233 R SUB X4, X4, X4 </span></p><p class="c14"><span class="c15">4 005102b3 R ADD </span><span class="c7">X5</span><span class="c15">, </span><span class="c15 c25">X2</span><span class="c0">, X5 &nbsp; &larr; ADD, RS1_ONLY case, RAW with inst 3 cycles ago</span></p><p class="c14"><span class="c15">5 00618333 R ADD X6, </span><span class="c15 c47">X3</span><span class="c0">, X6 &nbsp; &larr; ADD, RS1_ONLY case, RAW with inst 3 cycles ago</span></p><p class="c14"><span class="c15">6 0052c3b3 R XOR X7, </span><span class="c7">X5</span><span class="c15">, </span><span class="c7">X5</span><span class="c0">&nbsp; &nbsp;&larr; XOR, RS1AND2 case, &nbsp;RAW with inst 2 cycles ago</span></p><p class="c14 c10"><span class="c0"></span></p><p class="c4"><span style="overflow: hidden; display: inline-block; margin: 0.00px 0.00px; border: 0.00px solid #000000; transform: rotate(0.00rad) translateZ(0px); -webkit-transform: rotate(0.00rad) translateZ(0px); width: 715.00px; height: 89.00px;"><img alt="" src="images/image1.png" style="width: 715.00px; height: 89.00px; margin-left: 0.00px; margin-top: 0.00px; transform: rotate(0.00rad) translateZ(0px); -webkit-transform: rotate(0.00rad) translateZ(0px);" title=""></span></p><p class="c4 c10"><span class="c1"></span></p><p class="c4"><span>The expected inst_x_rs_case_x_cyc_apart coverage from the sequence of instructions is 2/225 = 0.88% and the simulator rounds down to the nearest tenth in this case.</span></p><h1 class="c32" id="h.y2c7jss61z8d"><span class="c21">Running riscv-vip unit tests</span></h1><p class="c4"><span class="c1">During development, unit testing of riscv-vip is done to improve quality and capture usage examples. &nbsp;Running and examining the unit tests is a great way to better understand the riscv-vip. &nbsp;Users can easily create their own unit tests to verify their understanding and the workings of the code.</span></p><p class="c4 c10"><span class="c1"></span></p><p class="c4"><span>The unit tests will have names of the form *_unit_test.sv. &nbsp;SVUnit is used for the unit testing framework, this can be obtained from </span><span class="c24 c35"><a class="c3" href="https://www.google.com/url?q=https://github.com/nosnhojn/svunit-code&amp;sa=D&amp;ust=1547000476260000">https://github.com/nosnhojn/svunit-code</a></span><span>. &nbsp;Follow the instructions posted there to install.</span></p><h2 class="c13" id="h.md8ehg2r1vjs"><span class="c34">Instruction unit tests</span></h2><p class="c4"><span class="c1">The instruction unit tests in the instruction_unit_test.sv file exercise and test the decoder and instruction use- cases and functional coverage.</span></p><p class="c4 c10"><span class="c1"></span></p><p class="c4"><span class="c1">With SVUnit is installed, the tests are run as follows, assuming you are in the riscv-vip/src directory:</span></p><p class="c4 c10"><span class="c1"></span></p><p class="c4"><span class="c0">% make inst_ut</span></p><p class="c4 c10"><span class="c1"></span></p><p class="c4"><span class="c1">By default, this will run using Modelsim. &nbsp;To run in Cadence ius, append SIMR=ius to the above command.</span></p><p class="c4 c10"><span class="c1"></span></p><p class="c4"><span class="c1">The output looks like this:</span></p><p class="c4 c10"><span class="c1"></span></p><p class="c2"><span class="c0">runSVUnit -t instruction_unit_test.sv -s modelsim &nbsp; -f riscv_vip.f </span></p><p class="c2"><span class="c0">SVUNIT: Output File: ./.__testsuite.sv</span></p><p class="c2"><span class="c0">SVUNIT: Creating class __testsuite:</span></p><p class="c2"><span class="c0">SVUNIT: Creating instances for:</span></p><p class="c2"><span class="c0">...</span></p><p class="c2"><span class="c0">-- Compiling module testrunner</span></p><p class="c2 c10"><span class="c0"></span></p><p class="c2"><span class="c0">Top level modules:</span></p><p class="c2"><span class="c0">&nbsp; &nbsp; &nbsp; &nbsp; testrunner</span></p><p class="c2"><span class="c0">End time: 17:08:06 on Jun 08,2018, Elapsed time: 0:00:00</span></p><p class="c2"><span class="c0">Errors: 0, Warnings: 2</span></p><p class="c2"><span class="c0">Reading pref.tcl</span></p><p class="c2 c10"><span class="c0"></span></p><p class="c2"><span class="c0"># 10.6c</span></p><p class="c2 c10"><span class="c0"></span></p><p class="c2"><span class="c0"># vsim -c -lib work -do &quot;run -all; quit&quot; -l run.log testrunner </span></p><p class="c2"><span class="c0"># Start time: 17:08:07 on Jun 08,2018</span></p><p class="c2"><span class="c0"># ** Note: (vsim-3813) Design is being optimized due to module recompilation...</span></p><p class="c2"><span class="c0"># ** Warning: hex_file_analyzer.sv(54): (vopt-2252) Missing incrementer in &quot;FOR&quot; statement.</span></p><p class="c2"><span class="c0"># // &nbsp;Questa Sim</span></p><p class="c2"><span class="c0"># // &nbsp;Version 10.6c linux Jul 25 2017</span></p><p class="c2"><span class="c0">...</span></p><p class="c2"><span class="c0"># run -all</span></p><p class="c2"><span class="c0"># INFO: &nbsp;[0][__ts]: Registering Unit Test Case inst32_ut</span></p><p class="c2"><span class="c0"># INFO: &nbsp;[0][testrunner]: Registering Test Suite __ts</span></p><p class="c2"><span class="c0"># INFO: &nbsp;[0][__ts]: RUNNING</span></p><p class="c2"><span class="c0"># INFO: &nbsp;[0][inst32_ut]: RUNNING</span></p><p class="c2"><span class="c0"># INFO: &nbsp;[0][inst32_ut]: ug_example1::RUNNING</span></p><p class="c2"><span class="c0"># My addi from code is [ fff08193 I ADDI X3_GP, X1_RA, -1 ]</span></p><p class="c2"><span class="c0"># INFO: &nbsp;[0][inst32_ut]: ug_example1::PASSED</span></p><p class="c2"><span class="c0"># INFO: &nbsp;[0][inst32_ut]: ug_example2::RUNNING</span></p><p class="c2"><span class="c0"># decode of 0xfff08193 is [ fff08193 I ADDI X3_GP, X1_RA, -1 ]</span></p><p class="c2"><span class="c0"># INFO: &nbsp;[0][inst32_ut]: ug_example2::PASSED</span></p><p class="c2"><span class="c0"># INFO: &nbsp;[0][inst32_ut]: test1::RUNNING</span></p><p class="c2"><span class="c0"># 0ff0a2f3 I CSRRS X5_T0, X1_RA, 255</span></p><p class="c2"><span class="c0"># 0010a133 R SLT X2_SP, X1_RA, X1_RA </span></p><p class="c2"><span class="c0"># INFO: &nbsp;[0][inst32_ut]: test1::PASSED</span></p><p class="c2"><span class="c0"># INFO: &nbsp;[0][inst32_ut]: inst32_sformat_cov::RUNNING</span></p><p class="c2"><span class="c0"># INFO: &nbsp;[0][inst32_ut]: inst32_sformat_cov::PASSED</span></p><p class="c2"><span class="c0"># INFO: &nbsp;[0][inst32_ut]: inst32_uformat_cov::RUNNING</span></p><p class="c2"><span class="c0"># INFO: &nbsp;[0][inst32_ut]: inst32_uformat_cov::PASSED</span></p><p class="c2"><span class="c0"># INFO: &nbsp;[0][inst32_ut]: inst32_jformat_cov::RUNNING</span></p><p class="c2"><span class="c0"># INFO: &nbsp;[0][inst32_ut]: inst32_jformat_cov::PASSED</span></p><p class="c2"><span class="c0"># INFO: &nbsp;[0][inst32_ut]: inst32_bformat_cov::RUNNING</span></p><p class="c2"><span class="c0"># INFO: &nbsp;[0][inst32_ut]: inst32_bformat_cov::PASSED</span></p><p class="c2"><span class="c0"># INFO: &nbsp;[0][inst32_ut]: inst32_iformat_cov::RUNNING</span></p><p class="c2"><span class="c0"># INFO: &nbsp;[0][inst32_ut]: inst32_iformat_cov::PASSED</span></p><p class="c2"><span class="c0"># INFO: &nbsp;[0][inst32_ut]: store_to_string::RUNNING</span></p><p class="c2"><span class="c0"># INFO: &nbsp;[0][inst32_ut]: store_to_string::PASSED</span></p><p class="c2"><span class="c0"># INFO: &nbsp;[0][inst32_ut]: PASSED (9 of 9 tests passing)</span></p><p class="c2"><span class="c0"># </span></p><p class="c2"><span class="c0"># INFO: &nbsp;[0][__ts]: PASSED (1 of 1 testcases passing)</span></p><p class="c2"><span class="c0"># </span></p><p class="c2"><span class="c0"># INFO: &nbsp;[0][testrunner]: PASSED (1 of 1 suites passing) [SVUnit v3.26]</span></p><p class="c2"><span class="c0"># ** Note: $finish &nbsp; &nbsp;: .testrunner.sv(40)</span></p><p class="c2"><span class="c0"># &nbsp; &nbsp;Time: 0 ns &nbsp;Iteration: 9 &nbsp;Instance: /testrunner</span></p><p class="c2"><span class="c0"># End time: 17:08:08 on Jun 08,2018, Elapsed time: 0:00:01</span></p><p class="c2"><span class="c0"># Errors: 0, Warnings: 1</span></p><p class="c4 c10"><span class="c1"></span></p><p class="c4"><span class="c1">Have a look into the instruction_unit_test.sv file to better understand what is going on here. &nbsp;</span></p><h2 class="c13" id="h.vfsts1ixyjl1"><span class="c34">Instruction History unit tests</span></h2><p class="c4"><span class="c1">The instruction history tests are run as follows, assuming you are in the riscv-vip/src directory:</span></p><p class="c4 c10"><span class="c1"></span></p><p class="c4"><span class="c0">% make ihist_ut</span></p><p class="c4 c10"><span class="c1"></span></p><a id="id.wltvbaiyij2j"></a><h2 class="c13" id="h.n6xp8fmn6aw1"><span class="c34">HEX file analyzer unit tests</span></h2><p class="c4"><span class="c1">The unit test for hex_file_analyzer.sv reads in a list of RV32UI HEX files from the riscv-tests project. &nbsp;It then dumps out the associated riscv-vip trace and also sampled coverage of every instruction in the HEX files. &nbsp;</span></p><p class="c4 c10"><span class="c1"></span></p><p class="c4"><span>The HEX files for RV32UI generated from the riscv-test project are committed to the riscv-vip repository. &nbsp;These files were generated from the riscv-test assembly files, as described by the </span><span class="c24 c38"><a class="c3" href="#h.vsxf66ih81vf">Generating the HEX files from source section</a></span><span>,</span><span class="c1">&nbsp;below. &nbsp;These files have been included for convenience so the user doesn&rsquo;t need to install the riscv-tools project.</span></p><p class="c4 c10"><span class="c1"></span></p><p class="c4"><span class="c1">Run the test as follows, &nbsp;assuming you are in the riscv-vip/src directory:</span></p><p class="c4 c10"><span class="c1"></span></p><p class="c2"><span class="c0">% make hex_ut</span></p><p class="c2 c10"><span class="c0"></span></p><p class="c4"><span class="c1">Observe a trace output scroll by, like shown below. &nbsp;</span></p><p class="c4 c10"><span class="c1"></span></p><p class="c2"><span class="c0">...</span></p><p class="c2"><span class="c0"># INFO: &nbsp;[0][hex_file_analyzer_ut]: analyze_hex_files::RUNNING</span></p><p class="c2"><span class="c0"># 00000000 04c0006f J JAL X0_ZERO, 76</span></p><p class="c2"><span class="c0"># 00000004 34202f73 I CSRRS X30_T5, X0_ZERO, 834</span></p><p class="c2"><span class="c0"># 00000008 00800f93 I ADDI X31_T6, X0_ZERO, 8</span></p><p class="c2"><span class="c0"># 0000000c 03ff0a63 B BEQ X30_T5, X31_T6 52</span></p><p class="c2"><span class="c0"># 00000010 00900f93 I ADDI X31_T6, X0_ZERO, 9</span></p><p class="c2"><span class="c0"># 00000014 03ff0663 B BEQ X30_T5, X31_T6 44</span></p><p class="c2"><span class="c0"># 00000018 00b00f93 I ADDI X31_T6, X0_ZERO, 11</span></p><p class="c2"><span class="c0"># 0000001c 03ff0263 B BEQ X30_T5, X31_T6 36</span></p><p class="c2"><span class="c0"># 00000020 00000f17 U AUIPC X30_T5, 0</span></p><p class="c2"><span class="c0"># 00000024 fe0f0f13 I ADDI X30_T5, X30_T5, -32</span></p><p class="c2"><span class="c0"># 00000028 000f0463 B BEQ X30_T5, X0_ZERO 8</span></p><p class="c2"><span class="c0">...</span></p><p class="c2"><span class="c0"># 000005c8 0011e193 I ORI X3_GP, X3_GP, 1</span></p><p class="c2"><span class="c0"># 000005cc 00000073 I ECALL X0_ZERO, X0_ZERO, 0</span></p><p class="c2"><span class="c0"># 000005d0 0ff0000f I FENCE X0_ZERO, X0_ZERO, 255</span></p><p class="c2"><span class="c0"># 000005d4 00100193 I ADDI X3_GP, X0_ZERO, 1</span></p><p class="c2"><span class="c0"># 000005d8 00000073 I ECALL X0_ZERO, X0_ZERO, 0</span></p><p class="c2"><span class="c0"># 000005dc c0001073 I CSRRW X0_ZERO, X0_ZERO, -1024</span></p><p class="c2"><span class="c0"># INFO: &nbsp;[0][hex_file_analyzer_ut]: analyze_hex_files::PASSED</span></p><p class="c2"><span class="c0"># INFO: &nbsp;[0][hex_file_analyzer_ut]: PASSED (1 of 1 tests passing)</span></p><p class="c2"><span class="c0"># </span></p><p class="c2"><span class="c0"># INFO: &nbsp;[0][__ts]: PASSED (1 of 1 testcases passing)</span></p><p class="c2"><span class="c0"># </span></p><p class="c2"><span class="c0"># INFO: &nbsp;[0][testrunner]: PASSED (1 of 1 suites passing) [SVUnit v3.26]</span></p><p class="c2"><span class="c0"># ** Note: $finish &nbsp; &nbsp;: .testrunner.sv(40)</span></p><p class="c2"><span class="c0"># &nbsp; &nbsp;Time: 0 ns &nbsp;Iteration: 1 &nbsp;Instance: /testrunner</span></p><p class="c2"><span class="c0"># Saving coverage database on exit...</span></p><p class="c2"><span class="c0"># End time: 18:49:58 on Jun 11,2018, Elapsed time: 0:00:12</span></p><p class="c2"><span class="c0"># Errors: 0, Warnings: 0</span></p><p class="c4 c10"><span class="c1"></span></p><p class="c4"><span class="c1">This is essentially the disassembly of each HEX file. These outputs can be cross referenced / checked against the related disassembly *.DUMP file produced the toolchain. &nbsp;</span></p><h3 class="c33" id="h.eo7whbwx6x75"><span class="c20">View the functional coverage of scanning the HEX files</span></h3><p class="c4"><span class="c1">The coverage scored by sampling HEX file instructions can be analyzed. &nbsp;It&rsquo;s important to note that this is not the way coverage is typically done in a verif env, yet it is an interesting experiment none-the-less. &nbsp;Any execution of these HEX programs would cover a subset of all instructions in the file as scored by the file analyzer. &nbsp;</span></p><p class="c4 c10"><span class="c1"></span></p><p class="c4"><span class="c1">The most interesting part is what is missing from the HEX file coverage -- this indicates things that cannot possibly be covered by running the program and potential areas where there could be bugs.</span></p><p class="c4 c10"><span class="c1"></span></p><p class="c4"><span class="c1">Run the following command, assuming you are in the riscv-vip/src directory and using QuestaSim:</span></p><p class="c2 c10"><span class="c0"></span></p><p class="c2"><span class="c0">% make cov</span></p><p class="c4 c10"><span class="c1"></span></p><p class="c4"><span class="c1">The Questa GUI should open. &nbsp;Goto Window &gt; Covergroups to browse the coverage of the different covergroups. &nbsp; For example, the following shows what instructions were observed.</span></p><p class="c4 c10"><span class="c1"></span></p><p class="c4"><span style="overflow: hidden; display: inline-block; margin: 0.00px 0.00px; border: 0.00px solid #000000; transform: rotate(0.00rad) translateZ(0px); -webkit-transform: rotate(0.00rad) translateZ(0px); width: 619.50px; height: 754.59px;"><img alt="" src="images/image3.png" style="width: 619.50px; height: 754.59px; margin-left: 0.00px; margin-top: 0.00px; transform: rotate(0.00rad) translateZ(0px); -webkit-transform: rotate(0.00rad) translateZ(0px);" title=""></span></p><h3 class="c33" id="h.frtdl08uxjvc"><span class="c20">Generating the HEX files from source, for the hex_file_analyzer</span></h3><p class="c4 c10"><span class="c1"></span></p><p class="c4"><span>To generate the RV32UI HEX files from the riscv-test project you must have the riscv-tools project installed from </span><span class="c24"><a class="c3" href="https://www.google.com/url?q=https://github.com/riscv/riscv-tools&amp;sa=D&amp;ust=1547000476273000">https://github.com/riscv/riscv-tools</a></span><span>, this contains the needed gcc compiler toolchain and also contains the riscv-tests as a submodule. &nbsp;The RISCV_TEST environment variable needs to point to your </span><span class="c24"><a class="c3" href="https://www.google.com/url?q=https://github.com/riscv/riscv-tests&amp;sa=D&amp;ust=1547000476274000">https://github.com/riscv/riscv-tests</a></span><span>&nbsp;installation. If you are installing riscv-tests be sure to follow the instructions in the riscv-tests README. &nbsp;The RISCV_TEST environment variable can be set by running the following in the </span><span class="c9">riscv-tests</span><span class="c1">&nbsp;install directory:</span></p><p class="c4 c10"><span class="c0"></span></p><p class="c2"><span class="c0">% export RISCV_TESTS=`pwd` </span></p><p class="c2 c10"><span class="c0"></span></p><p class="c4"><span class="c1">Now, from the root of your riscv-vip clone: </span></p><p class="c4 c10"><span class="c1"></span></p><p class="c2"><span class="c0">% cd riscv_tests_hexgen/</span></p><p class="c2"><span class="c0">% make clean </span></p><p class="c2"><span class="c0">% make </span></p><p class="c4 c10"><span class="c1"></span></p><p class="c4"><span class="c1">This hex_file_list target will:</span></p><ul class="c40 lst-kix_cm2k39g01xa0-0 start"><li class="c2 c18"><span class="c1">compile the elf, hex, and dump files for the many rv32ui arch assembly tests from the riscv-tests project</span></li><li class="c2 c18"><span class="c1">put output files into riscv_tests_hexgen/build dir</span></li><li class="c2 c18"><span class="c1">create riscv_test_hexgen/build/hex_files.txt, a list of hex files for the hex_file_analyzer class to process</span></li></ul><p class="c4 c10"><span class="c1"></span></p><p class="c4"><span>The new HEX files can be run through the hex_file_analyzer class as described in the </span><span class="c24"><a class="c3" href="#h.h2mk1dyhi6sq">HEX file analyzer unit tests</a></span><span>&nbsp;section. </span></p><a id="id.z55i9zkjkvbv"></a><h1 class="c32" id="h.usth6hj7su54"><span class="c21">Adding riscv-vip to an existing RISC-V core</span></h1><p class="c4"><span class="c1">This section is written assuming you have no existing UVM environment and that you want to passively add the riscv-vip to monitor and score coverage for your test. &nbsp;For those with existing UVM environments, the integration is similar but you will already have a UVM test in place. </span></p><h2 class="c13" id="h.tqcs6dcoa7z4"><span class="c34">Syntacore SCR1 riscv-vip integration demo project example</span></h2><p class="c4"><span>A demo repository and accompanying documentation has been created on GitHub to show how the riscv-vip can be instantiated and connected into the existing SCR1&rsquo;s non-UVM testbench and simulation environment. &nbsp;The project is located at </span><span class="c24"><a class="c3" href="https://www.google.com/url?q=https://github.com/jerralph/riscv-vip-scr1-demo&amp;sa=D&amp;ust=1547000476276000">https://github.com/jerralph/riscv-vip-scr1-demo</a></span><span class="c1">. This integration requires some glue logic since the SCR1 does not carry the instruction bits thru the pipeline and a lookup table is required to associate the instruction bits with the completed instruction at the writeback stage of the pipeline.</span></p><h2 class="c13" id="h.5snu4g694b5u"><span class="c34">General integration steps</span></h2><h3 class="c33" id="h.qmffeuqm764a"><span class="c20">Update your build process to compile and include riscv-vip files</span></h3><p class="c4"><span class="c1">Include the following files in your simulation build process, where riscv-vip is your clone of the riscv-vip repo. &nbsp;</span></p><p class="c4 c10"><span class="c1"></span></p><p class="c2"><span class="c0">riscv-vip/src/riscv_vip_pkg.sv</span></p><p class="c2"><span class="c0">riscv-vip/src/riscv_vip_class_pkg.sv</span></p><p class="c2"><span class="c15">riscv-vip/src/uvm/riscv_vip_uvc_pkg.sv</span></p><p class="c2"><span class="c0">riscv-vip/src/uvm/test/riscv_vip_test_pkg.sv</span></p><p class="c2 c10"><span class="c0"></span></p><p class="c4"><span class="c1">Add the following paths to the incdir so the *.svh files included by the pkg files can be located by the simulator.</span></p><p class="c4 c10"><span class="c1"></span></p><p class="c2"><span class="c0">riscv-vip/src</span></p><p class="c2"><span class="c0">riscv-vip/src/uvm</span></p><p class="c2"><span class="c15">riscv-vip/src/uvm</span><span class="c0">/test</span></p><h3 class="c33" id="h.cl9dy39kyl5w"><span class="c20">Update your testbench</span></h3><p class="c4"><span class="c1">In the module where you instantiate the design under test (DUT) -- generally the testbench or _tb file -- tap into instruction and address of the instructions executed on the RISC-V core you are using. &nbsp;Where and how this interface is connected depends on the implementation of the DUT and what the user wants to accomplish. &nbsp;</span></p><p class="c4 c10"><span class="c1"></span></p><p class="c4"><span class="c1">Ideally you tap into completed instructions from the final stage of the pipeline where the register file values are written back to the register file. &nbsp;Tapping into instruction from earlier stages can result in false coverage and trace data since instructions fetched in earlier stages of the pipeline may not actually be completed. &nbsp;For example, instructions following a conditional branch are a common cause of fetched instructions that don&rsquo;t get executed when branches are taken. </span></p><p class="c4 c10"><span class="c1"></span></p><p class="c4"><span class="c1">Some glue logic in the testbench may be needed to present only fully-completed instructions to the riscv-vip instruction interface. &nbsp;Some logic may be required to identify exactly when the instruction is completed. &nbsp;Also, some RISC-V implementations may not carry the raw instruction bits, as required by the riscv-vip instruction interface, into the later stages of the pipeline. &nbsp;In such cases, glue logic may be needed to lookup the instruction bits from the history of fetched instruction address and data. &nbsp;The open source Syntacore SCR1 riscv-vip demo integration is one example requiring and illustrating such glue logic.</span></p><p class="c4 c10"><span class="c1"></span></p><p class="c4"><span class="c1">Additionally, by sourcing the instruction interface values from completed instructions and resolving the rs1 and rs2 values from the register file at the time of completion, you should not need to be concerned values in the register file being stale for the instruction. &nbsp;If instructions were sample from earlier stages of the pipeline,register value forwarding would be required to accommodate data hazard cases where the register file values do not reflect the most recent to-be-written-back values of more mature instructions in the pipeline. Care must also be taken that the result of the instruction has not been written back and reflected into the register file before the source register values, rs1, and rs2, are resolved. &nbsp;Eventually/ideally a simple assembly program will be provided with the riscv-vip to test that the instruction and regfile are tapped/white-boxed correctly. &nbsp;</span></p><p class="c4 c10"><span class="c1"></span></p><p class="c4"><span class="c1">The instruction interface contains the following and is defined in the riscv_vip_inst_if.sv file:</span></p><p class="c4 c10"><span class="c1"></span></p><p class="c2"><span class="c0">interface riscv_vip_inst_if (input clk, input rstn);</span></p><p class="c2"><span class="c0">&nbsp; &nbsp;logic[31:0] curr_pc;</span></p><p class="c2"><span class="c0">&nbsp; &nbsp;logic [31:0] curr_inst; &nbsp; </span></p><p class="c2"><span class="c0">endinterface</span></p><p class="c4 c10"><span class="c1"></span></p><p class="c4"><span class="c1">The interface used to connect to the riscv-vip to the RTL values of the register file is in riscv_vip_regfile_if.sv , and looks as follows:</span></p><p class="c4 c10"><span class="c1"></span></p><p class="c2"><span class="c0">interface riscv_vip_regfile_if (input clk, input rstn);</span></p><p class="c2"><span class="c0">&nbsp; //NOTE regfile is 1-31 and index 0 is not included since it&#39;s always zero</span></p><p class="c2"><span class="c0">&nbsp; &nbsp;riscv_vip_pkg::x_regfile_array_t x;</span></p><p class="c2"><span class="c0">endinterface</span></p><p class="c4 c10"><span class="c1 c19"></span></p><p class="c4"><span class="c1">Update the testbench to import and include the needed items.</span></p><p class="c4 c10"><span class="c1"></span></p><p class="c2"><span class="c0">import uvm_pkg::*;</span></p><p class="c2"><span class="c0">import riscv_vip_uvc_pkg::*;</span></p><p class="c2"><span class="c0">import riscv_vip_test_pkg::*;</span></p><p class="c2 c10"><span class="c0"></span></p><p class="c2"><span class="c0">`include &quot;uvm_macros.svh&quot;</span></p><p class="c4 c10"><span class="c1"></span></p><p class="c4"><span>I</span><span class="c1">nstantiate the instruction and general purpose register file interface in the testbench and pass this as a virtual interface into the UVM world using the UVM configuration database, as shown by the code below. &nbsp;Again, recall that some glue logic may be needed in the testbench to only present fully completed instruction and pc to the riscv-vip interface -- such code is implementation specific and not shown here. &nbsp;Finally, at the end of the code segment to be added to the testbench, the UVM portion of the test is run. &nbsp;This will run alongside your pre-existing tests. &nbsp;Note that uvm_test_top.m_uvc_env is the hierarchical path to the reusable riscv-vip Universal Verification Component (UVC).</span></p><p class="c4 c10"><span class="c0"></span></p><p class="c4"><span class="c0">//riscv-vip virtual if instantiation</span></p><p class="c4"><span class="c15">riscv_vip_inst_if </span><span class="c0">rv_vip_inst_if(</span></p><p class="c4"><span class="c0">&nbsp; `SOME_XMR_TO_CORE.clk,</span></p><p class="c4"><span class="c0">&nbsp; `SOME_XMR_TO_CORE.rstn</span></p><p class="c4"><span class="c0">);</span></p><p class="c4 c10"><span class="c0"></span></p><p class="c4"><span class="c0">//use xmrs to connect up the interface</span></p><p class="c4"><span class="c0">assign rv_vip_inst_if.curr_pc = `SOME_XMR_TO_CORE.pc; &nbsp; &nbsp; &nbsp; </span></p><p class="c4"><span class="c0">assign rv_vip_inst_if.curr_inst = `SOME_XMR_TO_CORE.instr;</span></p><p class="c4 c10"><span class="c0"></span></p><p class="c4"><span class="c0">riscv_vip_regfile_if rv_vip_rf_if(</span></p><p class="c4"><span class="c0">&nbsp; `SOME_XMR_TO_CORE.clk,</span></p><p class="c4"><span class="c0">&nbsp; `SOME_XMR_TO_CORE.rstn</span></p><p class="c4"><span class="c0">);</span></p><p class="c4 c10"><span class="c0 c19"></span></p><p class="c4"><span class="c0">assign rv_vip_rf_if.x[01] = `SOME_XMR_TO_RF.x01;</span></p><p class="c4"><span class="c0">assign rv_vip_rf_if.x[02] = `SOME_XMR_TO_RF.x02;</span></p><p class="c4"><span class="c0">assign rv_vip_rf_if.x[03] = `SOME_XMR_TO_RF.x03;</span></p><p class="c4"><span class="c0">assign rv_vip_rf_if.x[04] = `SOME_XMR_TO_RF.x04;</span></p><p class="c4"><span class="c0">assign rv_vip_rf_if.x[05] = `SOME_XMR_TO_RF.x05;</span></p><p class="c4"><span class="c0">assign rv_vip_rf_if.x[06] = `SOME_XMR_TO_RF.x06;</span></p><p class="c4"><span class="c0">assign rv_vip_rf_if.x[07] = `SOME_XMR_TO_RF.x07;</span></p><p class="c4"><span class="c0">assign rv_vip_rf_if.x[08] = `SOME_XMR_TO_RF.x08;</span></p><p class="c4"><span class="c0">assign rv_vip_rf_if.x[09] = `SOME_XMR_TO_RF.x09;</span></p><p class="c4"><span class="c0">assign rv_vip_rf_if.x[10] = `SOME_XMR_TO_RF.x10;</span></p><p class="c4"><span class="c0">assign rv_vip_rf_if.x[11] = `SOME_XMR_TO_RF.x11;</span></p><p class="c4"><span class="c0">assign rv_vip_rf_if.x[12] = `SOME_XMR_TO_RF.x12;</span></p><p class="c4"><span class="c0">assign rv_vip_rf_if.x[13] = `SOME_XMR_TO_RF.x13;</span></p><p class="c4"><span class="c0">assign rv_vip_rf_if.x[14] = `SOME_XMR_TO_RF.x14;</span></p><p class="c4"><span class="c0">assign rv_vip_rf_if.x[15] = `SOME_XMR_TO_RF.x15;</span></p><p class="c4"><span class="c0">assign rv_vip_rf_if.x[16] = `SOME_XMR_TO_RF.x16;</span></p><p class="c4"><span class="c0">assign rv_vip_rf_if.x[17] = `SOME_XMR_TO_RF.x17;</span></p><p class="c4"><span class="c0">assign rv_vip_rf_if.x[18] = `SOME_XMR_TO_RF.x18;</span></p><p class="c4"><span class="c0">assign rv_vip_rf_if.x[19] = `SOME_XMR_TO_RF.x19;</span></p><p class="c4"><span class="c0">assign rv_vip_rf_if.x[20] = `SOME_XMR_TO_RF.x20;</span></p><p class="c4"><span class="c0">assign rv_vip_rf_if.x[21] = `SOME_XMR_TO_RF.x21;</span></p><p class="c4"><span class="c0">assign rv_vip_rf_if.x[22] = `SOME_XMR_TO_RF.x22;</span></p><p class="c4"><span class="c0">assign rv_vip_rf_if.x[23] = `SOME_XMR_TO_RF.x23;</span></p><p class="c4"><span class="c0">assign rv_vip_rf_if.x[24] = `SOME_XMR_TO_RF.x24;</span></p><p class="c4"><span class="c0">assign rv_vip_rf_if.x[25] = `SOME_XMR_TO_RF.x25;</span></p><p class="c4"><span class="c0">assign rv_vip_rf_if.x[26] = `SOME_XMR_TO_RF.x26;</span></p><p class="c4"><span class="c0">assign rv_vip_rf_if.x[27] = `SOME_XMR_TO_RF.x27;</span></p><p class="c4"><span class="c0">assign rv_vip_rf_if.x[28] = `SOME_XMR_TO_RF.x28;</span></p><p class="c4"><span class="c0">assign rv_vip_rf_if.x[29] = `SOME_XMR_TO_RF.x29;</span></p><p class="c4"><span class="c0">assign rv_vip_rf_if.x[30] = `SOME_XMR_TO_RF.x30;</span></p><p class="c4"><span class="c0">assign rv_vip_rf_if.x[31] = `SOME_XMR_TO_RF.x31;</span></p><p class="c4 c10"><span class="c0 c19"></span></p><p class="c4"><span class="c0">//CSR interface (currently not implemented, but things will error if not set into</span></p><p class="c4"><span class="c0">//config db)</span></p><p class="c4"><span class="c15">riscv_vip_csr_if rv_vip_csr_if(clk,rst_n);</span></p><p class="c4 c10"><span class="c0 c19"></span></p><p class="c4"><span class="c0">genvar core; </span></p><p class="c4"><span class="c0">generate</span></p><p class="c4"><span class="c0">&nbsp; for (core = 0; core &lt; `NUM_CORES; core++) begin : gen_cores</span></p><p class="c4"><span class="c0">&nbsp; &nbsp; const static string agent_xmr = $psprintf(&quot;uvm_test_top.m_uvc_env.m_i32_agent[%0d]&quot;,core);</span></p><p class="c4"><span class="c0">&nbsp; &nbsp; &nbsp; &nbsp; </span></p><p class="c4"><span class="c0">&nbsp; &nbsp; initial begin : set_riscv_vip_vif_to_db</span></p><p class="c4"><span class="c0">&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; </span></p><p class="c4"><span class="c0">&nbsp; &nbsp; &nbsp; uvm_config_db#(virtual riscv_vip_inst_if)::set(</span></p><p class="c4"><span class="c0">&nbsp; &nbsp; &nbsp; &nbsp; null,</span></p><p class="c4"><span class="c0">&nbsp; &nbsp; &nbsp; &nbsp; agent_xmr,</span></p><p class="c4"><span class="c0">&nbsp; &nbsp; &nbsp; &nbsp; &quot;m_vi&quot;,</span></p><p class="c4"><span class="c0">&nbsp; &nbsp; &nbsp; &nbsp; rv_vip_inst_if</span></p><p class="c4"><span class="c0">&nbsp; &nbsp; &nbsp; );</span></p><p class="c4 c10"><span class="c0"></span></p><p class="c4"><span class="c0">&nbsp; &nbsp; &nbsp; uvm_config_db#(virtual riscv_vip_regfile_if)::set(</span></p><p class="c4"><span class="c0">&nbsp; &nbsp; &nbsp; &nbsp; null,</span></p><p class="c4"><span class="c0">&nbsp; &nbsp; &nbsp; &nbsp; agent_xmr, </span></p><p class="c4"><span class="c0">&nbsp; &nbsp; &nbsp; &nbsp; &quot;m_rf_vi&quot;,</span></p><p class="c4"><span class="c0">&nbsp; &nbsp; &nbsp; &nbsp; rv_vip_rf_if</span></p><p class="c4"><span class="c0">&nbsp; &nbsp; &nbsp; );</span></p><p class="c4 c10"><span class="c0"></span></p><p class="c4"><span class="c0">&nbsp; &nbsp; &nbsp; uvm_config_db#(virtual riscv_vip_csr_if)::set(</span></p><p class="c4"><span class="c0">&nbsp; &nbsp; &nbsp; &nbsp; null,</span></p><p class="c4"><span class="c0">&nbsp; &nbsp; &nbsp; &nbsp; agent_xmr,</span></p><p class="c4"><span class="c0">&nbsp; &nbsp; &nbsp; &nbsp; &quot;m_csr_vi&quot;,</span></p><p class="c4"><span class="c0">&nbsp; &nbsp; &nbsp; &nbsp; rv_vip_csr_if</span></p><p class="c4"><span class="c0">&nbsp; &nbsp; &nbsp; );</span></p><p class="c4"><span class="c0">&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;</span></p><p class="c4"><span class="c0">&nbsp; &nbsp; &nbsp; uvm_config_db#(int)::set(</span></p><p class="c4"><span class="c0">&nbsp; &nbsp; &nbsp; &nbsp; null,</span></p><p class="c4"><span class="c0">&nbsp; &nbsp; &nbsp; &nbsp; agent_xmr,</span></p><p class="c4"><span class="c0">&nbsp; &nbsp; &nbsp; &nbsp; &quot;m_core_id&quot;,</span></p><p class="c4"><span class="c0">&nbsp; &nbsp; &nbsp; &nbsp; core</span></p><p class="c4"><span class="c0">&nbsp; &nbsp; &nbsp; &nbsp; );</span></p><p class="c4"><span class="c0">&nbsp; &nbsp; &nbsp; </span></p><p class="c4"><span class="c0">&nbsp; &nbsp; end &nbsp; &nbsp; &nbsp; </span></p><p class="c4"><span class="c0">&nbsp; end : gen_cores</span></p><p class="c4"><span class="c0">endgenerate</span></p><p class="c4 c10"><span class="c0"></span></p><p class="c4"><span class="c0">//Run UVM test</span></p><p class="c4"><span class="c0">initial begin</span></p><p class="c4"><span class="c15">&nbsp;</span><span class="c15">&nbsp;run_test();</span></p><p class="c4"><span class="c15">end</span></p><h3 class="c33" id="h.hk2zvn4lklf8"><span class="c20">Simulator flags</span></h3><p class="c4"><span class="c1">For Cadence ius the flags used are </span></p><p class="c4 c10"><span class="c1"></span></p><p class="c2"><span class="c0">-uvm -sv -exit +licq +nowarn+CUVWSP +nowarn+LIBNOU +nowarn+SPDUSD -linedebug -uvmlinedebug -coverage all -covoverwrite +define+DUMP+TRN +access+rc +UVM_TESTNAME=riscv_vip_base_test</span></p><p class="c4 c10"><span class="c1"></span></p><p class="c4"><span>Note that the +UVM_TEST_NAME is passed to the simulator at runtime, </span><span>as</span><span class="c1">&nbsp;a SystemVerilog plus argument. &nbsp; </span></p><p class="c4 c10"><span class="c1"></span></p><p class="c4"><span class="c1">For Mentor Questasim the flags are</span></p><p class="c2"><span class="c15 c38 c45">-mfcu -incr -sv &quot;+nowarn8233&quot; -warning vlog-2997 &quot;+acc&quot; -R -voptargs=&quot;+cover=bcefst&quot; -coverage -do &quot;coverage save -onexit coverage.ucdb&quot; UVM_TESTNAME=riscv_vip_base_test</span></p><h3 class="c33" id="h.fxza2dadr22z"><span class="c20">Locating the trace file</span></h3><p class="c4"><span class="c1">After running a simulation with the riscv_vip_base_test, if things are working correctly, you should find a trace file named riscv_tracker_&lt;core_id&gt;.log in the directory where the simulation is run.</span></p><p class="c4 c10"><span class="c1"></span></p></body></html>